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| 14-bit, 125 msps/105 msps/80 msps, 1.8 v analog-to-digital converter AD9255 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009C2010 analog devices, inc. all rights reserved. features snr = 78.3 dbfs @ 70 mhz and 125 msps sfdr = 93 dbc @ 70 mhz and 125 msps low power: 371 mw @ 125 msps 1.8 v analog supply operation 1.8 v cmos or lvds output supply integer 1-to-8 input clock divider if sampling frequencies to 300 mhz ?153.4 dbm/hz small signal input noise with 200 input impedance @ 70 mhz and 125 msps optional on-chip dither programmable internal adc voltage reference integrated adc sample-and-hold inputs flexible analog input range: 1 v p-p to 2 v p-p differential analog inputs with 650 mhz bandwidth adc clock duty cycle stabilizer serial port control user-configurable, built-in self-test (bist) capability energy-saving power-down modes applications communications multimode digital receivers (3g) gsm, edge, w-cdma, lte, cdma2000, wimax, and td-scdma smart antenna systems general-purpose software radios broadband data applications ultrasound equipment product highlights 1. on-chip dither option for improved sfdr performance with low power analog input. 2. proprietary differential input that maintains excellent snr performance for input frequencies up to 300 mhz. 3. operation from a single 1.8 v supply and a separate digital output driver supply accommodating 1.8 v cmos or lvds outputs. 4. standard serial port interface (spi) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock dcs, power-down, test modes, and voltage reference mode. 5. pin compatibility with the ad9265, allowing a simple migration up to 16 bits. functional block diagram 14 14 drvdd (1.8v) d13 to d0 oeb dco dither clk+ clk? sync clock management adc 14-bit core output staging cmos or lvds (ddr) vcm vref vin+ vin? track-and-hold reference rbias sense pdwn serial port svdd sclk/ dfs sdio/ dcs csb a gnd a vdd (1.8v) lvds lvds_rs AD9255 or 08505-001 figure 1.
AD9255 rev. a | page 2 of 44 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? product highlights ........................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? general description ......................................................................... 3 ? specifications ..................................................................................... 4 ? adc dc specifications ................................................................. 4 ? adc ac specifications ................................................................. 5 ? digital specifications ................................................................... 6 ? switching specifications ................................................................ 8 ? timing specifications .................................................................. 9 ? absolute maximum ratings .......................................................... 10 ? thermal characteristics ............................................................ 10 ? esd caution ................................................................................ 10 ? pin configurations and function descriptions ......................... 11 ? typical performance characteristics ........................................... 15 ? equivalent circuits ......................................................................... 23 ? theory of operation ...................................................................... 25 ? adc architecture ...................................................................... 25 ? analog input considerations .................................................... 25 ? voltage reference ....................................................................... 28 ? clock input considerations ...................................................... 29 ? power dissipation and standby mode .................................... 31 ? digital outputs ........................................................................... 32 ? timing ......................................................................................... 32 ? built-in self-test (bist) and output test .................................. 33 ? built-in self-test (bist) ............................................................ 33 ? output test modes ..................................................................... 33 ? serial port interface (spi) .............................................................. 34 ? configuration using the spi ..................................................... 34 ? hardware interface ..................................................................... 34 ? configuration without the spi ................................................ 35 ? spi accessible features .............................................................. 35 ? memory map .................................................................................. 36 ? reading the memory map register table ............................... 36 ? memory map register table ..................................................... 37 ? memory map register descriptions ........................................ 39 ? applications information .............................................................. 40 ? design guidelines ...................................................................... 40 ? outline dimensions ....................................................................... 41 ? ordering guide .......................................................................... 41 ? revision history 1/10rev. 0 to rev. a changes to worst other (harmonic or spur) parameter, table 2 ................................................................................................ 6 changes to figure 77 ...................................................................... 29 changes to input clock divider section ..................................... 30 changes to table 17 ........................................................................ 37 updated outline dimensions ....................................................... 41 10/09revision 0: initial version AD9255 rev. a | page 3 of 44 general description the AD9255 is a 14-bit, 125 msps analog-to-digital converter (adc). the AD9255 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired. the adc core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 14-bit accuracy at 125 msps data rates and guarantees no missing codes over the full operating temperature range. the adc features a wide bandwidth differential sample-and- hold analog input amplifier supporting a variety of user-selectable input ranges. it is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the nyquist rate. combined with power and cost savings over previously available adcs, the AD9255 is suitable for applications in communications, instrumentation, and medical imaging. a differential clock input controls all internal conversion cycles. a duty cycle stabilizer provides the means to compensate for vari- ations in the adc clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. an integrated voltage reference eases design considerations. the adc output data format is either parallel 1.8 v cmos or lvds (ddr). a data output clock is provided to ensure proper latch timing with receiving logic. programming for setup and control is accomplished using a 3-wire spi-compatible serial interface. flexible power-down options allow significant power savings, when desired. an optional on- chip dither function is available to improve sfdr performance with low power analog input signals. the AD9255 is available in a pb-free, 48-lead lfcsp and is specified over the industrial temperature range of ?40c to +85c. AD9255 rev. a | page 4 of 44 specifications adc dc specifications avdd = 1.8 v, drvdd = 1.8 v, svdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, d cs enabled, unless otherwise noted. table 1. parameter temp AD9255bcpz-80 1 AD9255bcpz-105 1 AD9255bcpz-125 1 unit min typ max min typ max min typ max resolution full 14 14 14 bits accuracy no missing codes full guarant eed guaranteed guaranteed offset error full 0.05 0.25 0.05 0.25 0.05 0.25 % fsr gain error full 0.2 2.5 0.2 2.5 0.4 2.5 % fsr differential nonlinearity (dnl) 2 full 0.4 0.4 0.45 lsb 25c 0.2 0.2 0.25 lsb integral nonlinearity (inl) 2 full 0.9 0.9 1.2 lsb 25c 0.35 0.45 0.7 lsb temperature drift offset error full 2 2 2 ppm/c gain error full 15 15 15 ppm/c internal voltage reference output voltage error (1 v mode) full +8 12 +8 12 +8 12 mv load regulation @ 1.0 ma full 3 3 3 mv input referred noise vref = 1.0 v 25c 0.62 0.63 0.61 lsb rms analog input input span, vref = 1.0 v full 22 2 v p-p input capacitance 3 full 88 8 pf input common-mode voltage full 0.9 0.9 0.9 v reference input resistance full 66 6 k power supplies supply voltage avdd full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v svdd full 1.7 3.5 1.7 3.5 1.7 3.5 v supply current iavdd 2 full 126 131 169 176 194 202 ma idrvdd 2 (1.8 v cmos) full 13 19 23 ma idrvdd 2 (1.8 v lvds) full 39 42 44 ma power consumption dc input full 239 248 321 332 371 382 mw sine wave input 2 cmos output mode full 252 338 391 mw lvds output mode full 306 384 437 mw standby power 4 full 54 54 54 mw power-down power full 0.05 0.15 0.05 0.15 0.05 0.15 mw 1 the suffix following the part number refers to the model found in the ordering guide section. 2 measured with a low input frequency, full-scale sine wa ve, with approximately 5 pf load ing on each output bit. 3 input capacitance refers to the effective capacitance between one differential input pin and agnd. 4 standby power is measured with a dc input, the clk pins (clk+, clk?) inactive (set to avdd or agnd). AD9255 rev. a | page 5 of 44 adc ac specifications avdd = 1.8 v, drvdd = 1.8 v, svdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, d cs enabled, unless otherwise noted. table 2. parameter 1 temp AD9255bcpz-80 2 AD9255bcpz-105 2 AD9255bcpz-125 2 unit min typ max min typ max min typ max signal-to-noise-ratio (snr) f in = 2.4 mhz 25c 79.2 78.9 78.3 dbfs f in = 70 mhz 25c 78.9 78.5 78.3 dbfs full 78.1 77.6 76.9 dbfs f in = 140 mhz 25c 78.0 77.7 77.1 dbfs f in = 200 mhz 25c 76.9 76.4 75.5 dbfs signal-to-noise-and distortion (sinad) f in = 2.4 mhz 25c 78.7 78.6 78.0 dbfs f in = 70 mhz 25c 78.7 78.0 78.0 dbfs full 77.9 77.3 76.7 dbfs f in = 140 mhz 25c 76.8 77.0 76.7 dbfs f in = 200 mhz 25c 75.8 75.3 74.3 dbfs effective number of bits (enob) f in = 2.4 mhz 25c 12.8 12.8 12.7 bits f in = 70 mhz 25c 12.8 12.7 12.7 bits f in = 140 mhz 25c 12.5 12.5 12.4 bits f in = 200 mhz 25c 12.3 12.2 12.0 bits worst second or third harmonic f in = 2.4 mhz 25c ?88 ?90 ?88 dbc f in = 70 mhz 25c ?94 ?89 ?93 dbc full ?91 ?88 ?85 dbc f in = 140 mhz 25c ?82 ?86 ?89 dbc f in = 200 mhz 25c ?81 ?81 ?80 dbc spurious-free dynamic range (sfdr) f in = 2.4 mhz 25c 88 90 88 dbc f in = 70 mhz 25c 94 89 93 dbc full 91 88 85 dbc f in = 140 mhz 25c 82 86 89 dbc f in = 200 mhz 25c 81 81 80 dbc spurious-free dynamic range (sfdr) without dither (ain @ ?23 dbfs) f in = 2.4 mhz 25c 102 99 96 dbfs f in = 70 mhz 25c 103 97 99 dbfs f in = 140 mhz 25c 104 97 98 dbfs f in = 200 mhz 25c 102 101 97 dbfs with on-chip dither (ain @ ?23 dbfs) f in = 2.4 mhz 25c 110 109 108 dbfs f in = 70 mhz 25c 110 108 109 dbfs f in = 140 mhz 25c 110 108 109 dbfs f in = 200 mhz 25c 110 109 109 dbfs AD9255 rev. a | page 6 of 44 parameter 1 temp AD9255bcpz-80 2 AD9255bcpz-105 2 AD9255bcpz-125 2 unit min typ max min typ max min typ max worst other (harmonic or spur) without dither f in = 2.4 mhz 25c ?106 ?105 ?101 dbc f in = 70 mhz 25c ?106 ?104 ?104 dbc full ?94 ?95 ?91 dbc f in = 140 mhz 25c ?104 ?104 ?103 dbc f in = 200 mhz 25c ?102 ?103 ?100 dbc with on-chip dither f in = 2.4 mhz 25c ?105 ?106 ?101 dbc f in = 70 mhz 25c ?106 ?105 ?104 dbc full ?97 ?99 ?98 dbc f in = 140 mhz 25c ?103 ?103 ?103 dbc f in = 200 mhz 25c ?100 ?101 ?100 dbc two-tone sfdr without dither f in = 29 mhz (?7 dbfs ), 32 mhz (?7 dbfs ) 25c 93 90 95 dbc f in = 169 mhz (?7 dbfs ), 172 mhz (?7 dbfs ) 25c 80 78 79 dbc analog input bandwidth 25c 650 650 650 mhz 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions. 2 the suffix following the part number refers to the model found in the section. ordering guide digital specifications avdd = 1.8 v, drvdd = 1.8 v, svdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, a nd dcs enabled, unless otherwise noted. table 3. parameter temperature min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl internal common-mode bias full 0.9 v differential input voltage full 0.3 3.6 v p-p input voltage range full agnd avdd v input common-mode range full 0.9 1.4 v high level input current full ?100 +100 a low level input current full ?100 +100 a input capacitance full 4 pf input resistance full 8 10 12 k sync input logic compliance cmos internal bias full 0.9 v input voltage range full agnd avdd v high level input voltage full 1.2 avdd v low level input voltage full agnd 0.6 v high level input current full ?100 +100 a low level input current full ?100 +100 a input capacitance full 1 pf input resistance full 12 16 20 k AD9255 rev. a | page 7 of 44 parameter temperature min typ max unit logic input (csb) 1 high level input voltage full 1.22 svdd v low level input voltage full 0 0.6 v high level input current full ?10 +10 a low level input current full 40 132 a input resistance full 26 k input capacitance full 2 pf logic input (sclk/dfs) 2 high level input voltage full 1.22 svdd v low level input voltage full 0 0.6 v high level input current (vin = 1.8 v) full ?92 ?135 a low level input current full ?10 +10 a input resistance full 26 k input capacitance full 2 pf logic input/output (sdio/dcs) 1 high level input voltage full 1.22 svdd v low level input voltage full 0 0.6 v high level input current full ?10 +10 a low level input current full 38 128 a input resistance full 26 k input capacitance full 5 pf high level output voltage full 1.70 v low level output voltage full 0.2 v logic inputs (oeb, pdwn, dither, lvds, lvds_rs) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current (vin = 1.8 v) full ?90 ?134 a low level input current full ?10 +10 a input resistance full 26 k input capacitance full 5 pf digital outputs (drvdd = 1.8 v) cmos mode high level output voltage i oh = 50 a full 1.79 v i oh = 0.5 ma full 1.75 v low level output voltage i ol = 1.6 ma full 0.2 v i ol = 50 a full 0.05 v lvds mode ansi mode differential output voltage (v od ) full 290 345 400 mv output offset voltage (v os ) full 1.15 1.25 1.35 v reduced swing mode differential output voltage (v od ) full 160 200 230 mv output offset voltage (v os ) full 1.15 1.25 1.35 v 1 pull-up. 2 pull-down. AD9255 rev. a | page 8 of 44 switching specifications avdd = 1.8 v, drvdd = 1.8 v, svdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, a nd dcs enabled, unless otherwise noted. table 4. AD9255bcpz-80 1 AD9255bcpz-105 1 AD9255bcpz-125 1 parameter temp min typ max min typ max min typ max unit clock input parameters input clock rate full 625 625 625 mhz conversion rate 2 dcs enabled full 20 80 20 105 20 125 msps dcs disabled full 10 80 10 105 10 125 msps clk perioddivide-by-1 mode (t clk ) full 12.5 9.5 8 ns clk pulse width high (t ch ) divide-by-1 mode dcs enabled full 3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 5.6 ns dcs disabled 5.9 6.25 6.6 4.5 4.75 5.0 3.8 4 4.2 ns divide-by-3 mode, divide-by-5 mode, and divide-by-7 mode, dcs enabled 3 full 0.8 0.8 0.8 ns divide-by-2 mode, divide-by-4 mode, divide- by-6 mode, and divide-by-8 mode, dcs enabled or dcs disabled 3 full 0.8 0.8 0.8 ns aperture delay (t a ) full 1.0 1.0 1.0 ns aperture uncertainty (jitter, t j ) full 0.07 0.07 0.07 ps rms data output parameters cmos mode data propagation delay (t pd ) full 2.4 2.8 3.4 2.4 2.8 3.4 2.4 2.8 3.4 ns dco propagation delay (t dco ) 4 full 2.7 3.4 4.2 2.7 3.4 4.2 2.7 3.4 4.2 ns dco to data skew (t skew ) full 0.3 0.6 0.9 0.3 0.6 0.9 0.3 0.6 0.9 ns pipeline delay (latency) full 12 12 12 cycles lvds mode data propagation delay (t pd ) full 2.6 3.4 4.2 2.6 3.4 4.2 2.6 3.4 4.2 ns dco propagation delay (t dco ) 4 full 3.3 3.8 4.3 3.3 3.8 4.3 3.3 3.8 4.3 ns dco to data skew (t skew ) ?0.3 +0.4 +1.2 ?0.3 +0.4 +1.2 ?0.3 +0.4 +1.2 pipeline delay (latency) full 12.5 12.5 12.5 cycles wake-up time 5 full 500 500 500 s out-of-range recovery time full 2 2 2 cycles 1 the suffix following the part number refers to the model found in the section. ordering guide 2 conversion rate is the clock rate after the divider. 3 see the section for additional info rmation on using the dcs with the input clock divider. input clock divider 4 additional dco delay can be added by writing to bit 0 through bit 4 in spi register 0x17 (see ). table 17 5 wake-up time is defined as the time required to return to normal operation from power-down mode. AD9255 rev. a | page 9 of 44 timing specifications table 5. parameter conditions min typ max unit sync timing requirements t ssync sync to rising edge of clk setup time 0.30 ns t hsync sync to rising edge of clk hold time 0.40 ns spi timing requirements 1 t ds setup time between the data and th e rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high sclk pulse width high 10 ns t low sclk pulse width low 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to th e sclk falling edge 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge 10 ns 1 refer to for a detailed timing diagram. figure 84 timing diagrams 08505-002 t dco t ch t cl t clk clk+ clk? dco? dco/dco+ d0/1+ to d12/d13+ lvds (ddr) mode d0/1? to d12/d13? cmos mode d0 to d13 n ? 1 n + 1 n + 2 n + 3 n + 5 n + 4 n vin t a t skew t pd dex ? 12 dox ? 12 dex ? 11 dox ? 11 dex ? 10 dox ? 10 dex ? 9 dox ? 9 dex ? 8 dox ? 8 dx ? 12 dx ? 11 dx ? 10 dx ? 9 dx ? 8 notes 1. dex denotes even bit. 2. dox denotes odd bit. figure 2. lvds (ddr) and cmos output mode data output timing sync clk+ t hsync t ssync 08505-104 figure 3. sync input timing requirements AD9255 rev. a | page 10 of 44 absolute maximum ratings table 6. parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to agnd ?0.3 v to +2.0v svdd to agnd ?0.3 v to +3.6 v vin+, vin? to agnd ?0.3 v to avdd + 0.2 v clk+, clk? to agnd ?0.3 v to avdd + 0.2 v sync to agnd ?0.3 v to avdd + 0.2 v vref to agnd ?0.3 v to avdd + 0.2 v sense to agnd ?0.3 v to avdd + 0.2 v vcm to agnd ?0.3 v to avdd + 0.2 v rbias to agnd ?0.3 v to avdd + 0.2 v csb to agnd ?0.3 v to svdd +0.3 v sclk/dfs to agnd ?0.3 v to svdd +0.3 v sdio/dcs to agnd ?0.3v to svdd + 0.3 v oeb to agnd ?0.3 v to drvdd + 0.2 v pdwn to agnd ?0.3 v to drvdd + 0.2 v lvds to agnd ?0.3 v to avdd + 0.2 v lvds_rs to agnd ?0.3 v to avdd + 0.2 v dither to agnd ?0.3 v to avdd + 0.2 v d0 through d13 to agnd ?0.3 v to drvdd + 0.2 v dco to agnd ?0.3 v to drvdd + 0.2 v environmental operating temperature range (ambient) ?40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the customer board increases the reliability of the solder joints and maximizes the thermal capability of the package. typical ja is specified for a 4-layer pcb with a solid ground plane. as shown, airflow improves heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the ja . table 7. thermal resistance package type airflow velocity (m/s) ja 1, 2 jc 1, 3 jb 1, 4 unit 48-lead lfcsp (cp-48-8) 0 24.5 1.3 12.7 c/w 1.0 21.4 c/w 2.5 19.2 c/w 1 per jedec 51-7, plus jede c 25-5 2s2p test board. 2 per jedec jesd51-2 (still air) or jedec jesd51-6 (moving air). 3 per mil-std 883, method 1012.1. 4 per jedec jesd51-8 (still air). esd caution AD9255 rev. a | page 11 of 44 13 14 15 16 17 18 19 20 21 22 23 24 drvdd d2 d3 d4 d5 d6 d7 drvdd d8 d9 d10 d11 48 47 46 45 44 43 42 41 40 39 38 37 pdwn rbias vcm avdd lvds vin? vin+ lvds_rs dnc dnc vref sense 1 2 3 4 5 6 7 8 9 10 11 12 sync clk+ clk? avdd avdd oeb dnc dco dnc dnc d0 (lsb) d1 dither avdd svdd csb sclk/dfs sdio/dcs drvdd dnc or d13 (msb) d12 35 avdd 36 34 33 32 31 30 29 28 27 26 25 AD9255 parallel cmos top view (not to scale) pin 1 indicator pin configurations and function descriptions notes 1. dnc = do not connect. 2. the exposed thermal pad on the bottom of the package provides the analog ground for the input. this exposed pad must be connected to ground for proper operation. 08505-003 figure 4. lfcsp parallel cmos pin configuration (top view) table 8. pin function descriptions (parallel cmos mode) pin no. mnemonic type description adc power supplies 13, 20, 29 drvdd supply digital outp ut driver supply (1.8 v nominal). 4, 5, 34, 36, 45 avdd supply analog power supply (1.8 v nominal). 33 svdd supply spi input/output voltage 7, 9, 10, 28, 39, 40 dnc do not connect. 0 agnd ground analog ground. the exposed thermal pad on the bottom of the package provides the analog ground for the input. this expos ed pad must be connected to ground for proper operation. adc analog 42 vin+ input differential analog input pin (+). 43 vin? input differential analog input pin (?). 38 vref input/output voltage reference input/output. 37 sense input voltage reference mode select. see table 11 for details. 47 rbias input/output external reference bias resistor. 46 vcm output common-mode level bias output for analog inputs. 2 clk+ input adc clock inputtrue. 3 clk? input adc clock inputcomplement. digital input 1 sync input digital synchronization pin. slave mode only. digital outputs 11 d0 (lsb) output cmos output data. 12 d1 output cmos output data. 14 d2 output cmos output data. 15 d3 output cmos output data. 16 d4 output cmos output data. 17 d5 output cmos output data. 18 d6 output cmos output data. 19 d7 output cmos output data. 21 d8 output cmos output data. AD9255 rev. a | page 12 of 44 pin no. mnemonic type description 22 d9 output cmos output data. 23 d10 output cmos output data. 24 d11 output cmos output data. 25 d12 output cmos output data. 26 d13 (msb) output cmos output data. 27 or output overrange output. 8 dco output data clock output. spi control 31 sclk/dfs input spi serial clock/data fo rmat select pin in external pin mode. 30 sdio/dcs input/output spi seri al data i/o/duty cycle stabiliz er pin in external pin mode. 32 csb input spi chip select (active low). adc configuration 6 oeb input output enable input (active low). 35 dither input in external pin mode, this pin sets dither to on (active high). pull low for control via spi in spi mode. 41 lvds_rs input in external pin mode, this pin sets lvds reduced swing output mode (active high). pull low for control via spi in spi mode. 44 lvds input in external pin mode, this pin sets lvds output mode (active high). pull low for control via spi in spi mode. 48 pdwn input power-down input in external pin mode. in spi mode, this input can be configured as power-down or standby. AD9255 rev. a | page 13 of 44 13 14 15 16 17 18 19 20 21 22 23 24 drvdd d2/3? d2/3+ d4/5? d4/5+ d6/7? d6/7+ drvdd d8/9? d8/9+ d10/11? d10/11+ 48 47 46 45 44 43 42 41 40 39 38 37 pdwn rbias vcm avdd lvds vin? vin+ lvds_rs dnc dnc vref sense 1 2 3 4 5 6 7 8 9 10 11 12 sync clk+ clk? avdd avdd oeb dco? dco+ dnc dnc d0/1? d0/1+ dither avdd svdd csb sclk/dfs sdio/dcs drvdd or+ or? d12/13+ d12/13? 35 avdd 36 34 33 32 31 30 29 28 27 26 25 AD9255 interleaved lvds top view (not to scale) pin 1 indicator notes 1. dnc = do not connect. 2. the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to ground for proper operation. 08505-004 figure 5. lfcsp interleaved parallel lvds pin configuration (top view) table 9. pin function descriptions (interleaved parallel lvds mode) pin no. mnemonic type description adc power supplies 13, 20, 29 drvdd supply digital outp ut driver supply (1.8 v nominal). 4, 5, 34, 36, 45 avdd supply analog power supply (1.8 v nominal). 33 svdd supply spi input/output voltage. 9, 10, 39, 40 dnc do not connect. 0 agnd ground analog ground. the exposed thermal pad on the bottom of the package provides the analog ground for the input. this exposed pa d must be connected to ground for proper operation. adc analog 42 vin+ input differential analog input pin (+). 43 vin? input differential analog input pin (?). 38 vref input/output voltage reference input/output. 37 sense input voltage reference mode select. see table 11 for details. 47 rbias input/output external reference bias resistor. 46 vcm output common-mode level bias output for analog inputs. 2 clk+ input adc clock inputtrue. 3 clk? input adc clock inputcomplement. digital input 1 sync input digital synchronization pin. slave mode only. digital outputs 12 d0/1+ output lvds output data bit 0/bit 1 (lsb)true. 11 d0/1? output lvds output data bit 0/bit 1 (lsb)complement. 15 d2/3+ output lvds output data bit 2/bit 3true. 14 d2/3? output lvds output data bit 2/bit 3complement. 17 d4/5+ output lvds output data bit 4/bit 5true. 16 d4/5? output lvds output data bit 4/bit 5complement. 19 d6/7+ output lvds output data bit 6/bit 7true. 18 d6/7? output lvds output data bit 6/bit 7complement. 22 d8/9+ output lvds output data bit 8/bit 9 true. 21 d8/9? output lvds output data bit 8/bit 9complement. AD9255 rev. a | page 14 of 44 pin no. mnemonic type description 24 d10/11+ output lvds output data bit 10/bit 11true. 23 d10/11? output lvds output data bit 10/bit 11complement. 26 d12/13+ (msb) output lvds output data bit 12/bit 13true. 25 d12/13? (msb) output lvds outp ut data bit 12/bit 13complement. 28 or+ output lvds overrange outputtrue. 27 or? output lvds overrange outputcomplement. 8 dco+ output lvds data clock outputtrue. 7 dco? output lvds data clock outputcomplement. spi control 31 sclk/dfs input spi serial clock/data fo rmat select pin in external pin mode. 30 sdio/dcs input/output spi seri al data i/o/duty cycle stabiliz er pin in external pin mode. 32 csb input spi chip select (active low). adc configuration 6 oeb input output enable input (active low). 35 dither input in external pin mode, this pin sets dither to on (active high). pull low for control via spi in the spi mode. 41 lvds_rs input in external pin mode, this pin sets lvds reduced swing output mode (active high). pull low for control via spi in the spi mode. 44 lvds input in external pin mode, this pin sets lvds o utput mode (active high). pull low for control via spi in the spi mode. 48 pdwn input power-down input in external pin mode. in spi mode, this input can be configured as power-down or standby. AD9255 rev. a | page 15 of 44 0 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, svdd = 1.8 v, sample rate = 125 msps, dcs enabled, 1.0 v internal reference, 2 v p-p differential input, vin = ?1.0 dbfs, and 32k sample, t a = 25c, unless otherwise noted. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 1 02 03 04 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 80msps 2.4mhz @ ?1dbfs snr = 78.2db (79.2dbfs) sfdr = 89dbc 08505-106 figure 6. AD9255-80 single-tone fft with f in = 2.4 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 1 02 03 04 amplitude (dbfs) frequency (mhz) 0 second harmonic 80msps 70.1mhz @ ?1dbfs snr = 77.8db (78.8dbfs) sfdr = 93.6dbc third harmonic 08505-107 figure 7. AD9255-80 single-tone fft with f in = 70.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 1 02 03 04 amplitude (dbfs) frequency (mhz) 0 80msps 140.1mhz @ ?1dbfs snr = 77.0db (78.0dbfs) sfdr = 82.1dbc third harmonic second harmonic 08505-108 figure 8. AD9255-80 single-tone fft with f in = 140.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 1 02 03 04 amplitude (dbfs) frequency (mhz) 0 80msps 200.3mhz @ ?1dbfs snr = 75.9db (76.9dbfs) sfdr = 81dbc third harmonic second harmonic 08505-109 figure 9. AD9255-80 single-tone fft with f in = 200.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 1 02 03 04 amplitude (dbfs) frequency (mhz) 0 80msps 70.1mhz @ ?6dbfs snr = 73.2db (79.2dbfs) sfdr = 99dbc third harmonic second harmonic 08505-110 figure 10. AD9255-80 single-tone fft with f in = 70.1 mhz @ ?6 dbfs with dither enabled 120 100 80 60 40 20 0 ?100 ?80?90 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbc and dbfs) input amplitude (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) sfdr (dbfs) 08505-111 figure 11. AD9255-80 single-tone snr/sfdr vs. input amplitude (a in ) with f in = 98.12 mhz AD9255 rev. a | page 16 of 44 120 110 100 90 80 70 ?100 ?80?90 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbfs) input amplitude (dbfs) sfdrfs (dither on) sfdrfs (dither off) snrfs (dither on) snrfs (dither off) 08505-112 figure 12. AD9255-80 single-tone snr/sfdr vs. input amplitude (a in ) with f in = 30 mhz with and without dither enabled 100 95 90 85 80 75 70 65 0 50 100 150 200 250 300 snr/sfdr (dbfs/dbc) input frequency (mhz) snr @ ?40c snr @ +25c snr @ +85c sfdr @ ?40c sfdr @ +25c sfdr @ +85c 08505-113 figure 13. AD9255-80 sing le-tone snr/sfdr vs. input frequency (f in ) and temperature with 2 v p-p full scale 105 100 95 90 85 80 75 25 8075706560555045403530 snr/sfdr (dbfs/dbc) sample rate (msps) sfdr snr 08505-114 figure 14. AD9255-80 single-ton e snr/sfdr vs. sample rate (f s ) with f in = 70.1 mhz 1.6m 1.4m 1.2m 1.0m 800k 600k 400k 200k 0 number of hits output code n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 0.62 lsb rms 08505-115 figure 15. AD9255-80 grounded input histogram 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 inl error (lsb) output code inl without dither inl with dither 08505-116 figure 16. AD9255-80 inl with f in = 12.5 mhz 0.50 ?0.50 ?0.25 0 0.25 dnl error (lsb) output code 08505-117 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 figure 17. AD9255-80 dnl with f in = 12.5 mhz AD9255 rev. a | page 17 of 44 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0102030 50 40 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 105msps 2.4mhz @ ?1dbfs snr = 77.9db (78.9dbfs) sfdr = 91dbc 08505-118 figure 18. AD9255-105 single-tone fft with f in = 2.4 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0102030 50 40 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 105msps 70.1mhz @ ?1dbfs snr = 77.4db (78.4dbfs) sfdr = 88.7dbc 08505-119 figure 19. AD9255-105 single-tone fft with f in = 70.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0102030 50 40 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 105msps 140.1mhz @ ?1dbfs snr = 76.7db (77.7dbfs) sfdr = 86.4dbc 08505-120 figure 20. AD9255-105 single-tone fft with f in = 140.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0102030 50 40 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 105msps 200.3mhz @ ?1dbfs snr = 75.4db (76.4dbfs) sfdr = 81.6dbc 08505-121 figure 21. AD9255-105 single-tone fft with f in = 200.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0102030 50 40 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 105msps 70.1mhz @ ?6dbfs snr = 72.9db (78.9dbfs) sfdr = 91dbc 08505-122 figure 22. AD9255-105 single-tone fft with f in = 70.1 mhz @ ?6 dbfs with dither enabled 120 100 80 60 40 20 0 ?100 ?80?90 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbc and dbfs) input amplitude (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) sfdr (dbfs) 08505-123 figure 23. AD9255-105 single-ton e snr/sfdr vs. input amplitude (a in ) with f in = 98.12 mhz AD9255 rev. a | page 18 of 44 120 110 100 90 80 70 ?100 ?80?90 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbfs) input amplitude (dbfs) sfdrfs (dither on) sfdrfs (dither off) snrfs (dither on) snrfs (dither off) 08505-124 figure 24. AD9255-105 single-ton e snr/sfdr vs. input amplitude (a in ) with f in = 30 mhz with and without dither enabled 100 95 90 85 80 75 70 65 0 50 100 150 200 250 300 snr/sfdr (dbfs/dbc) input frequency (mhz) snr @ ?40c snr @ +25c snr @ +85c sfdr @ ?40c sfdr @ +25c sfdr @ +85c 08505-125 figure 25. AD9255-105 single-tone snr/sfdr vs. input frequency (f in ) and temperature with 2 v p-p full scale 105 100 95 90 85 80 75 25 105 95857565 100 90 807060 555045403530 snr/sfdr (dbfs/dbc) sample rate (msps) sfdr snr 08505-126 figure 26. AD9255-105 single-tone snr/sfdr vs. sample rate (f s ) with f in = 70.1 mhz 1.4m 1.2m 1.0m 800k 600k 400k 200k 0 number of hits output code n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 0.63 lsb rms 08505-127 figure 27. AD9255-105 grounded input histogram 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 inl error (lsb) output code inl without dither inl with dither 08505-128 figure 28. AD9255-105 inl with f in = 12.5 mhz 0.50 ?0.50 ?0.25 0 0.25 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 dnl error (lsb) output code 08505-129 figure 29. AD9255-105 dnl with f in = 12.5 mhz AD9255 rev. a | page 19 of 44 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030 60 50 40 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 125msps 2.4mhz @ ?1dbfs snr = 77.2db (78.2dbfs) sfdr = 88dbc 08505-130 figure 30. AD9255-125 single-tone fft with f in = 2.4 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030 60 50 40 amplitude (dbfs) frequency (mhz) 125msps 30.3mhz @ ?1dbfs snr = 77.7db (78.7dbfs) sfdr = 95dbc 08505-131 second harmonic third harmonic figure 31. AD9255-125 single-tone fft with f in = 30.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030 60 50 40 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 125msps 70.1mhz @ ?1dbfs snr = 77.3db (78.3dbfs) sfdr = 93.9dbc 08505-132 figure 32. AD9255-125 single-tone fft with f in = 70.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030 60 50 40 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 125msps 140.1mhz @ ?1dbfs snr = 76.2db (77.2dbfs) sfdr = 88.9dbc 08505-133 figure 33. AD9255-125 single-tone fft with f in = 140.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030 60 50 40 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 125msps 200.3mhz @ ?1dbfs snr = 74.5db (75.5dbfs) sfdr = 80.0dbc 08505-134 figure 34. AD9255-125 single-tone fft with f in = 200.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030 60 50 40 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 125msps 220.1mhz @ ?1dbfs snr = 74.2db (75.2dbfs) sfdr = 79.8dbc 08505-135 figure 35. AD9255-125 single-tone fft with f in = 220.1 mhz AD9255 rev. a | page 20 of 44 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030 60 50 40 amplitude (dbfs) frequency (mhz) second harmonic third harmonic 125msps 70.1mhz @ ?6dbfs snr = 72.6db (78.6dbfs) sfdr = 99.7dbc 08505-136 figure 36. AD9255-125 single-tone fft with f in = 70.1 mhz @ ?6 dbfs with dither enabled 0 ?135 ?120 ?105 ?90 ?75 ?60 ?45 ?30 ?15 605448423630241812 6 amplitude (dbfs) frequency (mhz) + 2 5 3 4 6 08505-137 125msps 70.1mhz @ ?23dbfs snr = 56.4dbc (79.4dbfs) sfdr = 75.8dbc figure 37. AD9255-125 single-tone fft with f in = 70.1 mhz @ ?23 dbfs with dither disabled, 1m sample 0 ?135 ?120 ?105 ?90 ?75 ?60 ?45 ?30 ?15 605448423630241812 6 amplitude (dbfs) frequency (mhz) + 2 5 3 4 6 08505-138 125msps 70.1mhz @ ?23dbfs snr = 55.9dbc (78.9dbfs) sfdr = 86.6dbc figure 38. AD9255-125 single-tone fft with f in = 70.1 mhz @ ?23 dbfs with dither enabled, 1m sample 120 100 80 60 40 20 0 ?100 ?80?90 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbc and dbfs) input amplitude (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) sfdr (dbfs) 08505-139 figure 39. AD9255-125 single-ton e snr/sfdr vs. input amplitude (a in ) with f in = 2.4 mhz 120 100 80 60 40 20 0 ?100 ?80?90 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbc and dbfs) input amplitude (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) sfdr (dbfs) 08505-140 figure 40. AD9255-125 single-ton e snr/sfdr vs. input amplitude (a in ) with f in = 98.12 mhz 120 110 100 90 80 70 ?100 ?80?90 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbfs) input amplitude (dbfs) sfdrfs (dither on) sfdrfs (dither off) snrfs (dither on) snrfs (dither off) 08505-141 figure 41. AD9255-125 single-ton e snr/sfdr vs. input amplitude (a in ) with f in = 30 mhz with and without dither enabled AD9255 rev. a | page 21 of 44 100 95 90 85 80 75 70 65 0 50 100 150 200 250 300 snr/sfdr (dbfs/dbc) input frequency (mhz) snr @ ?40c snr @ +25c snr @ +85c sfdr @ ?40c sfdr @ +25c sfdr @ +85c 08505-142 figure 42. AD9255-125 single-tone snr/sfdr vs. input frequency (f in ) and temperature with 2 v p-p full scale 95 90 85 80 75 70 65 03 0 0 250 200 150 100 50 snr/sfdr (dbfs/dbc) input frequency (mhz) sfdr snr 08505-143 figure 43. AD9255-125 single-tone snr/sfdr vs. input frequency (f in ) with 1 v p-p full scale 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?90 ?6 ?18 ?30 ?42 ?54 ?66 ?78 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 08505-144 figure 44. AD9255-125 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 29.1 mhz, f in2 = 32.1 mhz, f s = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?90 ?6 ?18 ?30 ?42 ?54 ?66 ?78 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 08505-145 figure 45. AD9255-125 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 169.1 mhz, f in2 = 172.1 mhz, f s = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030 60 50 40 amplitude (dbfs) frequency (mhz) 125msps 29.1mhz @ ?7dbfs 32.1mhz @ ?7dbfs sfdr = 94.4dbc (101.4dbfs) 08505-146 figure 46. AD9255-125 two-tone fft with f in1 = 29.1 mhz and f in2 = 32.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030 60 50 40 amplitude (dbfs) frequency (mhz) 125msps 169.1mhz @ ?7dbfs 172.1mhz @ ?7dbfs sfdr = 79.5dbc (86.5dbfs) 08505-147 figure 47. AD9255-125 two-tone fft with f in1 = 169.1 mhz and f in2 = 172.1 mhz AD9255 rev. a | page 22 of 44 105 100 95 90 85 80 75 25 12511510595857565554535 snr/sfdr (dbfs/dbc) sample rate (msps) sfdr snr 08505-148 figure 48. AD9255-125 single-tone snr/sfdr vs. sample rate (f s ) with f in = 70.1 mhz 1.4m 1.2m 1.0m 800k 600k 400k 200k 0 number of hits output code n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 0.63 lsb rms 08505-149 figure 49. AD9255-125 grounded input histogram 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 inl error (lsb) output code inl without dither inl with dither 08505-150 figure 50. AD9255-125 inl with f in = 12.5 mhz 0.50 ?0.50 ?0.25 0 0.25 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 dnl error (lsb) output code 08505-151 figure 51. AD9255-125 dnl with f in = 12.5 mhz 100 90 80 70 60 50 40 0.75 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 snr/sfdr (dbfs and dbc) input common-mode voltage (v) sfdr (dbc) sfdr (dbfs) 08505-152 figure 52. AD9255-125 snr/sfdr vs. input common mode (vcm) with f in = 30 mhz AD9255 rev. a | page 23 of 44 equivalent circuits vin+ or vin? 08505-005 figure 53. equivalent analog input circuit avdd clk+ clk? 0.9v 10k? 10k? 08505-006 figure 54. equivalent clock input circuit 6k? avdd vref 08505-012 figure 55. equivalent vref circuit 350? avdd s ense 08505-010 figure 56. equivalent sense circuit drvdd pad 08505-007 figure 57. digital output 26k? 350? svdd s dio/dcs 0 8505-008 figure 58. equivalent sdio/dcs circuit 26k ? 350? svdd sclk/dfs 08505-009 figure 59. equivalent sclk/dfs input circuit 26k ? 350 ? svdd csb 08505-011 figure 60. equivalent csb input circuit AD9255 rev. a | page 24 of 44 26k ? 350? 08505-061 pdwn figure 61. equivalent pdwn circuit 26k? 350? drvdd oeb 0 8505-062 figure 62. equivalent oeb input circuit 26k ? 350? a vdd dither, lvds or lvds_rs 08505-063 figure 63. equivalent dither, lvds, and lvds_rs input circuit AD9255 rev. a | page 25 of 44 theory of operation with the AD9255, the user can sample any f s /2 frequency segment from dc to 200 mhz, using appropriate low-pass or band-pass filtering at the adc inputs with little loss in adc performance. operation to 300 mhz analog input is permitted, but occurs at the expense of increased adc noise and distortion. synchronization capability is provided to allow synchronized timing between multiple devices. programming and control of the AD9255 are accomplished using a 3-wire spi-compatible serial interface. adc architecture the AD9255 architecture consists of a front-end sample-and- hold input network, followed by a pipelined, switched-capacitor adc. the quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched-capacitor digital- to-analog converter (dac) and an interstage residue amplifier. the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage can be ac- or dc-coupled in differential or single-ended modes. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. during power-down, the output buffers go into a high impedance state. analog input considerations the analog input to the AD9255 is a differential switched- capacitor network that has been designed for optimum performance while processing a differential input signal. the clock signal alternatively switches between sample mode and hold mode (see figure 64 ). when the input is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within 1/2 of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low-pass filter at the adc input; therefore, the precise values are dependent on the application. in intermediate frequency (if) undersampling applications, any shunt capacitors should be reduced. in combination with the driving source impedance, the shunt capacitors limit the input bandwidth. refer to an-742 application note, frequency domain response of switched-capacitor adcs ; an-827 application note, a resonant approach to interfacing amplifiers to switched-capacitor adcs ; and the analog dialogue article, transformer-coupled front-end for wideband a/d converters, for more information on this subject (see www.analog.com ). c par1 c par1 c par2 c par2 s s s s s s c fb c fb c s c s bias bias v in+ h v in? 08505-037 figure 64. switche d-capacitor input for best dynamic performance, the source impedances driving vin+ and vin? should be matched, and the inputs should be differentially balanced. an internal differential reference buffer creates positive and negative reference voltages that define the input span of the adc core. the span of the adc core is set by this buffer to 2 vref . input common mode the analog inputs of the AD9255 are not internally dc biased. in ac-coupled applications, the user must provide this bias externally. setting the device so that v cm = 0.5 avdd is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see figure 52 ). an on-board common-mode voltage reference is included in the design and is available from the vcm pin. optimum performance is achieved when the common-mode voltage of the analog input is set by the vcm pin voltage (typically 0.5 avdd). the vcm pin must be decoupled to ground by a 0.1 f capacitor, as described in the applications information section. AD9255 rev. a | page 26 of 44 dither the AD9255 has an optional dither mode that can be selected either using the dither pin or using the spi bus. dithering is the act of injecting a known but random amount of white noise, commonly referred to as dither, into the input of the adc. dithering has the effect of improving the local linearity at various points along the adc transfer function. dithering can significantly improve the sfdr when quantizing small signal inputs, typically when the input level is below ?6 dbfs. as shown in figure 65 , the dither that is added to the input of the adc through the dither dac is precisely subtracted out digitally to minimize snr degradation. when dithering is enabled, the dither dac is driven by a pseudorandom number generator (pn gen). in the AD9255, the dither dac is precisely calibrated to result in only a very small degradation in snr and sinad. the typical snr and sinad degradation values, with dithering enabled, are only 1 db and 0.8 db, respectively. adc core dither dac pn gen dither enable v in dout 08505-038 figure 65. dither block diagram large signal fft in most cases, dithering does not improve sfdr for large signal inputs close to full scale, for example, with a ?1 dbfs input. for large signal inputs, the sfdr is typically limited by front-end sampling distortion, which dithering cannot improve. however, even for such large signal inputs, dithering may be useful for certain applications because it makes the noise floor whiter. as is common in pipeline adcs, the AD9255 contains small dnl errors caused by random component mismatches that produce spurs or tones that make the noise floor somewhat randomly colored part-to-part. although these tones are typically at very low levels and do not limit sfdr when the adc is quantizing large-signal inputs, dithering converts these tones to noise and produces a whiter noise floor. small signal fft for small signal inputs, the front-end sampling circuit typically contributes very little distortion, and, therefore, the sfdr is likely to be limited by tones caused by dnl errors due to random com- ponent mismatches. therefore, for small signal inputs (typically, those below ?6 dbfs), dithering can significantly improve sfdr by converting these dnl tones to white noise. static linearity dithering also removes sharp local discontinuities in the inl transfer function of the adc and reduces the overall peak-to- peak inl. in receiver applications, utilizing dither helps to reduce dnl errors that cause small signal gain errors. often, this issue is overcome by setting the input noise at 5 db to 10 db above the converter noise. by utilizing dither within the converter to correct the dnl errors, the input noise requirement can be reduced. differential input configurations optimum performance is achieved while driving the AD9255 in a differential input configuration. for baseband applications, the ad8138 , ada4937-2 , and ada4938-2 differential drivers provide excellent performance and a flexible interface to the adc. the output common-mode voltage of the ada4938-2 is easily set with the vcm pin of the AD9255 (see figure 66 ), and the driver can be configured in the filter topology shown to provide band limiting of the input signal. v in 76.8 ? 120? 0.1f 200 ? 200? 90? avdd 33 ? 33 ? 15? 15? 5pf 15pf 15pf adc vin? vin+ vcm ada4938-2 08505-039 figure 66. differential input configuration using the ada4938-2 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration. an example is shown in figure 67 . to bias the analog input, the vcm voltage can be connected to the center tap of the secondary winding of the transformer. 2v p-p 49.9 ? 0.1f r1 r1 c1 adc vin+ vin? vcm c2 r2 r2 c2 08505-040 figure 67. differential transformer-coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz (mhz). excessive signal power can also cause core saturation, which leads to distortion. at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the AD9255. for applications in AD9255 rev. a | page 27 of 44 table 10. example rc network which snr is a key parameter, differential double balun coupling is the recommended input configuration (see figure 68 ). in this configuration, the input is ac-coupled and the cml is provided to each input through a 33 resistor. these resistors compensate for losses in the input baluns to provide a 50 impedance to the driver. frequency range (mhz) r1 series ( each) c1 differential (pf) r2 series ( each) c2 shunt (pf each) 0 to 100 15 18 15 open 100 to 300 10 10 10 10 an alternative to using a transformer-coupled input at frequencies in the second nyquist zone and higher is to use the adl5562 differential driver. the adl5562 provides three selectable gain options up to 15.5 db. an example circuit is shown in figure 69 ; additional filtering between the adl5562 output and the AD9255 input may be required to reduce out-of-band noise. see the adl 5562 data sheet for more information. in the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input fre- quency and source impedance and may need to be reduced or removed. table 10 displays recommended values to set the rc network. however, these values are dependent on the input signal and should be used only as a starting guide. adc r1 0.1f c2 0.1f vin+ vin? vcm c1 c2 r1 r2 r2 0.1f s 0.1f 2 v p- p 33? 33? s p a p 08505-041 figure 68. differential double balun input configuration adl5562 0 ? 0.1f 0 ? 0.1f 0.1f 0.1f 2 1 3 11 0.1f 0.1f 10 9 v cc 0.1f 5, 6, 7, 8 100 ? 100 ? a nalog input a nalog input 5pf 15? AD9255 vin+ vin? vcm 08505-042 15? 15? 20? 20? 15? 10pf 10pf 4 figure 69. differential input configuration using the adl5562 AD9255 rev. a | page 28 of 44 voltage reference a stable and accurate voltage reference is built into the AD9255. the input range can be adjusted by varying the reference voltage applied to the AD9255, using either the internal reference or an externally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. the various reference modes are summarized in the sections that follow. the reference decoupling section describes the best practices pcb layout of the reference. internal reference connection a comparator within the AD9255 detects the potential at the sense pin and configures the reference into four possible modes, which are summarized in table 11 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 70 ), setting vref to 1.0 v for a 2.0 v p-p full- scale input. in this mode, with sense grounded, the full scale can also be adjusted through the spi port by adjusting bit 6 and bit 7 of register 0x18. these bits can be used to change the full scale to 1.25 v p-p, 1.5 v p-p, 1.75 v p-p, or to the default of 2.0 v p-p, as shown in table 17 . connecting the sense pin to the vref pin switches the reference amplifier output to the sense pin, completing the loop and providing a 0.5 v reference output for a 1 v p-p full-scale input. vref sense 0.5v adc select logic 0.1f 1.0f vin? vin+ adc core 0 8505-043 figure 70. internal reference configuration if a resistor divider is connected external to the chip, as shown in figure 71 , the switch again sets to the sense pin. this puts the reference amplifier in a noninverting mode with the vref output defined as follows: ? ? ? ? ? ? += 15.0 the input range of the adc always equals twice the voltage at the reference pin for either an internal or an external reference. 0.5v adc select logic vin? vin+ adc core vref sense 0.1f 1.0f r2 r1 0 8505-044 figure 71. programmable reference configuration if the internal reference of the AD9255 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 72 shows how the internal reference voltage is affected by loading. 0 8505-045 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 load current (ma) reference voltage error (%) vref = 1v vref = 0.5v figure 72. vref accuracy vs. load table 11. reference configuration summary selected mode sense voltage resulting vref (v) resulting differential span (v p-p) external reference avdd n/a 2 external reference internal fixed reference vref 0.5 1.0 programmable reference 0.2 v to vref ? ? ? ? ? ? + r1 r2 10.5 (see figure 71 ) 2 vref internal fixed reference agnd to 0.2 v 1.0 2.0 AD9255 rev. a | page 29 of 44 external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac- teristics. figure 73 shows the typical drift characteristics of the internal reference in 1.0 v mode. 08505-046 0.5 1.0 1.5 2.0 0 ?0.5 ?1.0 ?1.5 ?2.0 ?40 ?20 0 20 40 60 80 temperature (c) reference voltage error (mv) vref = 1.0v figure 73. typical vref drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 6 k load (see figure 55 ). the internal buffer generates the positive and negative full-scale references for the adc core. therefore, the external reference must be limited to a maximum of 1.0 v. clock input considerations for optimum performance, the AD9255 sample clock inputs, clk+ and clk?, should be clocked with a differential signal. the signal is typically ac-coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally (see figure 74 ) and require no external bias. avdd clk+ 4pf 4pf clk? 0.9v 0 8505-047 figure 74. equivalent clock input circuit clock input options the AD9255 has a very flexible clock input structure. clock input can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 75 and figure 76 show two preferred methods for clocking the AD9255. a low jitter clock source is converted from a single- ended signal to a differential signal using either an rf transformer or an rf balun. the rf balun configuration is recommended for clock frequencies at 625 mhz and the rf transformer is recommended for clock frequencies from 10 mhz to 200 mhz. the back-to-back schottky diodes across the transformer/balun secondary limit clock excursions into the AD9255 to approximately 0.8 v p-p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9255 while preserving the fast rise and fall times of the signal that are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100 ? clk? clk+ adc AD9255 mini-circuits ? adt1-1wt, 1:1z xfmr 0 8505-048 figure 75. transformer-coupled differential clock (up to 200 mhz) 0.1f 0.1f 1nf clock input 1nf 50 ? clk? clk+ schottky diodes: hsms2822 adc AD9255 08505-049 figure 76. balun-coupled differential clock (625 mhz) if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 77 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 / ad9518 / ad9520 / ad9522 clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? pecl driver 50k ? 50k ? clk? clk+ clock input clock input ad95xx adc AD9255 08505-050 figure 77. differential pecl sample clock (up to rated sample rate) AD9255 rev. a | page 30 of 44 100 ? 0.1f 0.1f 0.1f 0.1f 50k ? 50k? clk? clk+ clock input clock input ad95xx lvds driver adc AD9255 08505-051 figure 78. differential lvds sample clock (up to the rated sample rate) a third option is to ac couple a differential lvds signal to the sample clock input pins, as shown in figure 78 . the ad9510 / ad9511/ ad9512 / ad9513 / ad9514/ ad9515 / ad9516 / ad9517 / ad9518/ ad9520 / ad9522 clock drivers offer excellent jitter performance. in some applications, it may be acceptable to drive the sample clock inputs with a single-ended cmos signal. in such applica- tions, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor (see figure 79 ). optional 100 ? 0.1f 0.1f 0.1f 50? 1 1 50 ? resistor is optional. clk? clk+ v cc 1k ? 1k ? clock input ad95xx cmos driver adc AD9255 08505-052 figure 79. single-ended 1.8 v cmos input clock (up to 200 mhz) clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD9255 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9255. noise and distortion perform- ance are nearly flat for a wide range of duty cycles with the dcs enabled. jitter in the rising edge of the input is still of paramount concern and is not easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates less than 20 mhz nominally. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during the time period that the loop is not locked, the dcs loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the duty cycle stabilizer. the dcs can also be disabled in some cases when using the input clock divider circuit, see the input clock divider section for addi- tional information. in all other applications, enabling the dcs circuit is recommended to maximize ac performance. the dcs is enabled by setting the sdio/dcs pin high when operating in the external pin mode (see table 12 ). if the spi mode is enabled, the dcs is enabled by default and can be disabled by writing a 0x00 to address 0x09. input clock divider the AD9255 contains an input clock divider with the ability to divide the input clock by integer values between 2 and 8. for clock divide ratios of 2, 4, 6, or 8, the duty cycle stabilizer (dcs) is not required because the output of the divider inherently pro- duces a 50% duty cycle. enabling the dcs with the clock divider in these divide modes may cause a slight degradation in snr so disabling the dcs is recommended. for other divide ratios, divide-by-3, divide-by-5, and divide-by-7 the duty cycle output from the clock divider is related to the input clocks duty cycle. in these modes, if the input clock has a 50% duty cycle, the dcs is again not required. however, if a 50% duty cycle input clock is not available the dcs must be enabled for proper part operation. to synchronize the AD9255 clock divider, use an external sync signal applied to the sync pin. bit 1 and bit 2 of register 0x100 allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid signal at the sync pin causes the clock divider to reset to its initial state. this synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simulta- neous input sampling. if the sync pin is not used, it should be tied to agnd. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr from the low fre- quency snr (snr lf ) at a given input frequency (f input ) due to jitter (t jrms ) can be calculated by snr hf = ?10 log[(2 f input t jrms ) 2 + 10 ] )10/( lf snr in this equation, the rms aperture jitter represents the clock input jitter specification. if undersampling applications are particularly sensitive to jitter, as illustrated in figure 80 . AD9255 rev. a | page 31 of 44 80 75 70 65 60 55 50 1 10 100 1k input frequency (mhz) snr (dbc) measured 0.05ps 0.20ps 0.50ps 1.00ps 1.50ps 08505-053 figure 80. snr vs. input frequency and jitter treat the clock input as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9255. to avoid modulating the clock signal with digital noise, separate power supplies for clock drivers from the adc output driver supplies. low jitter, crystal controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or another method), the output clock should be retimed by the original clock at the last step. refer to an-501 application note, aperture uncertainty and adc system performance, and an-756 application note, sampled systems and the effects of clock phase noise and jitter (see www.analog.com ) for more information about jitter performance as it relates to adcs. power dissipation and standby mode as shown in figure 81 , the power dissipated by the AD9255 is proportional to its sample rate. in cmos output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. the maximum drvdd current (idrvdd) can be approximately calculated as idrvdd = vdrvdd c load f clk n where n is the number of output bits (14 output bits plus one dco). this maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the nyquist frequency of f clk /2. in practice, the drvdd current is established by the average number of output bits switching, which is deter- mined by the sample rate and the characteristics of the analog input signal. reducing the capacitive load presented to the output drivers can minimize digital power consumption. the data in figure 81 , figure 82 , and figure 83 was taken using a 70 mhz analog input signal, with a 5 pf load on each output driver. 0.5 total power idrvdd iavdd 0.4 0.3 0.2 0.1 0 0.20 0.16 0.12 0.08 0.04 0 25 125 75 100 50 total power (w) supply current (a) clock frequency (msps) 08505-179 figure 81. AD9255-125 power and current vs. sample rate 0.5 0.4 0.3 0.2 0.1 0 0.20 0.16 0.12 0.08 0.04 0 25 105 95 85 75 65 55 45 35 total power (w) supply current (a) clock frequency (msps) total power idrvdd iavdd 08505-180 figure 82. AD9255-105 power and current vs. sample rate 0.5 0.4 0.3 0.2 0.1 0 0.15 0.12 0.09 0.06 0.03 0 25 75 65 55 45 35 total power (w) supply current (a) encode frequency (msps) iavdd total power idrvdd 08505-181 figure 83. AD9255-80 power and current vs. sample rate by asserting pdwn (either through the spi port or by asserting the pdwn pin high), the AD9255 is placed in power-down mode. in this state, the adc typically dissipates 0.05 mw. during power-down, the output drivers are placed in a high impedance state; asserting the pdwn pin low returns the AD9255 to its normal operating mode. AD9255 rev. a | page 32 of 44 low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power- down mode and then must be recharged when returning to normal operation. when using the spi port interface, the user can place the adc in power-down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. in addition, when using the spi mode, the user can change the function of the external pdwn pin to either place the part in power-down or standby mode. see the memory map register descriptions section for more details. digital outputs the AD9255 output drivers can be configured to interface with 1.8 v cmos logic families. the AD9255 can also be configured for lvds outputs using a drvdd supply voltage of 1.8 v. the AD9255 defaults to cmos output mode but can be placed into lvds mode either by setting the lvds pin high or by using the spi port to place the part into lvds mode. because most users do not toggle between cmos and lvds mode during operation, use of the lvds pin is recommended to avoid any power-up loading issues on the cmos configured outputs. in cmos output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause current glitches on the supplies, which may affect converter performance. applications requiring the adc to drive large capacitive loads or large fanouts may require external buffers or latches. in lvds output mode, two output drive levels can be selected, either ansi lvds or reduced swing lvds mode. using the reduced swing lvds mode lowers the drvdd current and reduces power consumption. the reduced swing lvds mode can be selected by asserting the lvds_rs pin or by selecting this mode via the spi port. the output data format is selected for either offset binary or twos complement by setting the sclk/dfs pin when operating in the external pin mode (see table 12 ). as detailed in an-877 application note, interfacing to high speed adcs via spi , the data format can be selected for offset binary, twos complement, or gray code when using the spi control. table 12. sclk/dfs mode selection (external pin mode) voltage at pin sclk/dfs sdio/dcs agnd offset binary (default) dcs disabled svdd twos complement dcs enabled (default) digital output enable function (oeb) the AD9255 has a flexible three-state ability for the digital output pins. the three-state mode is enabled using the oeb pin or through the spi interface. if the oeb pin is low, the output data drivers and dcos are enabled. if the oeb pin is high, the output data drivers and dcos are placed in a high impedance state. this oeb function is not intended for rapid access to the data bus. note that oeb is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. when using the spi interface, the data and dco outputs can be three-stated by using the output enable bar bit in register 0x14. timing the AD9255 provides latched data with a pipeline delay of 12 clock cycles (12.5 clock cycles in lvds mode). data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. minimize the length of the output data lines and loads placed on them to reduce transients within the AD9255. these tran- sients can degrade converter dynamic performance. the lowest typical conversion rate of the AD9255 is 10 msps. at clock rates below 10 msps, dynamic performance can degrade. data clock output (dco) the AD9255 provides a single data clock output (dco) pin in cmos output mode and two differential data clock output (dco) pins in lvds mode intended for capturing the data in an external register. in cmos output mode, the data outputs are valid on the rising edge of dco, unless the dco clock polarity has been changed via the spi. in lvds output mode, data is output as double data rate with the even numbered output bits transitioning near the rising edge of dco and the odd numbered output bits transitioning near the falling edge of dco. see figure 2 for a graphical timing description. table 13. output data format input (v) condition (v) offset binary output mode twos complement mode or vin+ ? vin? < ?vref ? 0.5 lsb 00 0000 0000 0000 10 0000 0000 0000 1 vin+ ? vin? = ?vref 00 0000 0000 0000 10 0000 0000 0000 0 vin+ ? vin? = 0 10 0000 0000 0000 00 0000 0000 0000 0 vin+ ? vin? = +vref ? 1.0 lsb 11 1111 1111 1111 01 1111 1111 1111 0 vin+ ? vin? > +vref ? 0.5 lsb 11 1111 1111 1111 01 1111 1111 1111 1 AD9255 rev. a | page 33 of 44 built-in self-test (bist) and output test the AD9255 includes built-in self-test features designed to enable verification of the integrity of the part as well as facilitate board level debugging. a built-in self-test (bist) feature is included that verifies the integrity of the digital datapath of the AD9255. various output test options are also provided to place predictable values on the outputs of the AD9255. built-in self-test (bist) the bist is a thorough test of the digital portion of the selected AD9255 signal path. when enabled, the test runs from an internal pseudorandom noise (pn) source through the digital datapath starting at the adc block output. the bist sequence runs for 512 cycles and stops. the bist signature value is placed in register 0x24 and register 0x25. the outputs are not disconnected during this test, so the pn sequence can be observed as it runs. the pn sequence can be continued from its last value or reset from the beginning, based on the value programmed in register 0x0e, bit 2. the bist signature result varies based on the part configuration. output test modes the output test options are shown in table 17 . when an output test mode is enabled, the analog section of the adc is discon- nected from the digital back end blocks and the test pattern is run through the output formatting block. some of the test patterns are subject to output formatting, and some are not. the seed value for the pn sequence tests can be forced if the pn reset bits are used to hold the generator in reset mode by setting bit 4 or bit 5 of register 0x0d. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for more information, see an-877 application note, interfacing to high speed adcs via spi . AD9255 rev. a | page 34 of 44 serial port interface (spi) the AD9255 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to, or read from, via the port. memory is organized into bytes that can be further divided into fields, which are docu- mented in the memory map section. for detailed operational information, see an-877 application note, interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk/dfs pin, the sdio/dcs pin, and the csb pin (see table 14 ). the sclk/dfs (a serial clock) is used to synchronize the read and write data presented from and to the adc. the sdio/dcs (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal adc memory map registers. the csb (chip select bar) is an active low control that enables or disables the read and write cycles. table 14. serial port interface pins pin mnemonic function sclk/dfs serial clock. the sclk function of the pin is for the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio/dcs sdio is the serial data input/output function of the pin. a dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active low control that gates the read and write cycles. the falling edge of the csb, in conjunction with the rising edge of the sclk, determines the start of the framing. see figure 84 and table 5 for an example of the serial timing and its definitions. other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow for additional external timing. when csb is tied high at power-up, spi functions are placed in high impedance mode. this mode turns on any spi pin secondary functions. when csb is toggled low after power-up, the part remains in spi mode and does not revert back to pin mode. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. all data is composed of 8-bit words. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. this allows the serial data input/output (sdio) pin to change direction from an input to an output. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. if the instruction is a readback operation, performing a readback causes the serial data input/ output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb-first mode or in lsb-first mode. msb first is the default on power-up and can be changed via the spi port configuration register. for more information about this and other features, see an-877 application note, interfacing to high speed adcs via spi . hardware interface the pins described in table 14 comprise the physical interface between the user programming device and the serial port of the AD9255. when using the spi interface, the sclk pin and the csb pin function as inputs. the sdio pin is bidirectional, func- tioning as an input during write phases and as an output during readback. the AD9255 has a separate supply pin for the spi interface, svdd. the svdd pin can be set at any level between 1.8 v and 3.3 v to enable operation with a spi bus at these voltages without requiring level translation. if the spi port is not used, svdd can be tied to the drvdd voltage. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in an-812 application note, microcontroller- based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9255 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods. some pins serve a dual function when the spi interface is not being used. when the pins are tied to avdd or ground during device power-on, they are associated with a specific function. the digital outputs section describes the alternate functions that are supported on the AD9255. AD9255 rev. a | page 35 of 44 configuration without the spi in applications that do not interface to the spi control registers, the sdio/dcs pin and the sclk/dfs pin serve as standalone cmos-compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer and output data format feature control. in this mode, connect the csb chip select to avdd, which disables the serial port interface. the oeb pin, the dither pin, the lvds pin, the lvds_rs pin, and the pdwn pin are active control lines in both external pin mode and spi mode. the input from these pins or the spi register setting (the logical or of the spi bit and the pin function) is used to determine the mode of operation for the part. table 15. mode selection pin external voltage configuration sdio/dcs svdd (default) duty cycle stabilizer enabled agnd duty cycle stabilizer disabled sclk/dfs svdd twos complement enabled agnd (default) offset binary enabled oeb drvdd outputs in high impedance agnd (default) outputs enabled pdwn avdd chip in power-down or standby mode agnd (default) normal operation lvds agnd (default) cmos output mode avdd lvds output mode lvds_rs agnd (default) ansi lvds output levels avdd reduced swing lvds output levels dither agnd (default) dither disabled avdd dither enabled spi accessible features table 16 provides a brief description of the general features that are accessible via the spi. these features are described in detail in an-877 application note, interfacing to high speed adcs via spi . the AD9255 part-specific features are described in detail following tabl e 17 , the external memory map register table. table 16. features accessible using the spi feature name description mode allows the user to set either power-down mode or standby mode clock allows the user to access the dcs, set the clock divider, set the clock divider phase, and enable the sync input offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set the output mode output phase allows the user to set the output clock polarity output delay allows the user to vary the dco delay vref allows the user to set the reference voltage don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 08505-055 figure 84. serial port interface timing diagram AD9255 rev. a | page 36 of 44 memory map reading the memory map register table each row in the memory map register table has eight bit locations. the memory map is roughly divided into four sections: the chip configuration registers (address 0x00 to address 0x02); the transfer register (address 0xff); the adc functions registers, including setup, control, and test (address 0x08 to address 0x30); and the digital feature control registers (address 0x100). the memory map register table (see tabl e 17 ) documents the default hexadecimal value for each hexadecimal address shown. the column with the heading, bit 7 (msb), is the start of the default hexadecimal value given. for example, address 0x18, the vref select register, has a hexadecimal default value of 0xc0. this means that bit 7 = 1, bit 6 = 1, and the remaining bits are 0s. this setting is the default reference selection setting. the default value uses a 2.0 v p-p reference. for more information on this function and others, see an-877 application note, interfacing to high speed adcs via spi. this document details the functions controlled by register 0x00 to register 0x30. the remaining register, at register 0x100, is documented in the memory map register descriptions section. open locations all address and bit locations that are not included in table 17 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x18). if the entire address location is open (for example, address 0x13), this address location should not be written. default values after the AD9255 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table, table 17 . logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x08 to address 0x18 are shadowed. writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. this allows these registers to be updated internally and simulta- neously when the transfer bit is set. the internal update takes place when the transfer bit is set, and the bit autoclears. AD9255 rev. a | page 37 of 44 memory map register table all address and bit locations that are not included in table 17 are not currently supported for this device. table 17. memory map registers addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 0x00 spi port configuration 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 the nibbles are mirrored so lsb-first mode or msb-first mode registers correctly, regardless of shift mode 0x01 chip id 8-bit chip id[7:0], ad 9255 = 0x65 (default) 0x65 read only 0x02 chip grade open open speed grade id open open open open speed grade id used to differentiate devices; read only 01 = 125 msps 10 = 105 msps 11 = 80 msps transfer register 0xff transfer open open open open open open open transfer 0x00 synchronously transfers data from the master shift register to the slave adc functions registers 0x08 power modes 1 open external power- down pin function open open open internal power-down mode 0x80 determines various generic modes of chip operation 0 = power- down 00 = normal operation 1 = standby 01 = full power- down 10 = standby 11 = normal operation 0x09 global clock open open open open open open open duty cycle stabilizer (default) 0x01 0x0d test mode open open reset pn23 generator reset pn9 generator open output test mode 0x00 when this register is set, the test data is placed on the output pins in place of normal data 000 = off (default) 001 = midscale short 010 = positive fs 011 = negative fs 100 = alternating checkerboard 101 = pn 23 sequence 110 = pn 9 sequence 111 = one/zero word toggle 0x0e bist enable open open open open open reset bist sequence open bist enable 0x04 AD9255 rev. a | page 38 of 44 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x14 output mode drive strength output type open output enable bar open output invert output format 0x00 configures the outputs and the format of the data 0 = ansi lvds 0 = cmos 00 = offset binary 1 = reduced lvds 1 = lvds 01 = twos complement 01 = gray code 11 = offset binary 0x16 clock phase control invert dco clock open open open open input clock divider phase adjust 0x00 allows selection of clock delays into the input clock divider 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x17 dco output delay open open open dco clock delay 0x00 ( delay = 2500 ps register value /31) 00000 = 0 ps 00001 = 81 ps 00010 = 161 ps 11110 = 2419 ps 11111 = 2500 ps 0x18 vref select reference voltage selection open open open open open open 0xc0 00 = 1.25 v p-p 01 = 1.5 v p-p 10 = 1.75 v p-p 11 = 2.0 v p-p (default) 0x24 bist signature lsb bist signature[7:0] 0x00 read only 0x25 bist signature msb bist signature[15:8] 0x00 read only 0x30 dither enable open open open dither enable open open open open 0x00 digital feature control register 0x100 sync control open open open open open clock divider next sync only clock divider sync enable master sync enable 0x00 AD9255 rev. a | page 39 of 44 memory map register descriptions for additional information about functions controlled in register 0x00 to register 0xff, see an-877 application note, interfacing to high speed adcs via spi . sync control (register 0x100) bitsreserved these bits are reserved. bit 2clock divider next sync only if the master sync enable bit (address 0x100, bit 0) and the clock divider sync enable bit (address 0x100, bit 1) are high, bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. the clock divider sync enable bit (address 0x100, bit 1) resets after it syncs. bit 1clock divider sync enable bit 1 gates the sync pulse to the clock divider. the sync signal is enabled when bit 1 is high and bit 0 is high. this is continuous sync mode. bit 0master sync enable bit 0 must be high to enable any of the sync functions. if the sync capability is not used, this bit should remain low to conserve power. AD9255 rev. a | page 40 of 4 4 applications information design guidelines before starting design and layout of the AD9255 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins. power and ground recommendations when connecting power to the AD9255, it is recommended that two separate 1.8 v supplies be used. use one supply for analog (avdd); use a separate supply for the digital outputs (drvdd). several different decoupling capacitors can be used to cover both high and low frequencies. locate these capacitors close to the point of entry at the pcb level and close to the pins of the part, with minimal trace length. the power supply for the spi port, svdd, should not contain excessive noise and should also be bypassed close to the part. a single pcb ground plane should be sufficient when using the AD9255. with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. lvds operation the AD9255 can be configured for cmos or lvds output mode on power-up using the lvds pin, pin 44. if lvds operation is desired, connect pin 44 to avdd. lvds operation can also be enabled through the spi port. if cmos operation is desired, connect pin 44 to agnd. exposed paddle thermal heat slug recommendations it is mandatory that the exposed paddle on the underside of the adc be connected to the analog ground (agnd) to achieve the best electrical and thermal performance. a continuous, exposed (no solder mask) copper plane on the pcb should mate to the AD9255 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. fill or plug these vias with nonconductive epoxy. to maximize the coverage and adhesion between the adc and the pcb, overlay a silkscreen to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. for detailed information about packaging and pcb layout of chip scale packages, see the an-772 application note, a design and manufacturing guide for the lead frame chip scale package (lfcsp) , at www.analog.com . vcm decouple the vcm pin to ground with a 0.1 f capacitor, as shown in figure 67 . rbias the AD9255 requires that a 10 k resistor be placed between the rbias pin and ground. this resistor sets the master current reference of the adc core and should have at least a 1% tolerance. reference decoupling decouple the vref pin externally to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter per- formance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9255 to keep these signals from transitioning at the converter inputs during critical sampling periods. AD9255 rev. a | page 41 of 4 4 outline dimensions * compliant to jedec standards mo-220-vkkd-2 with exception to exposed pad dimension. 120109-b for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 48 12 13 37 36 24 25 * 5.65 5.50 sq 5.35 0.50 0.40 0.30 0.30 0.23 0.18 0.80 max 0.65 typ 5.50 ref coplanarity 0.08 exposed pad (bottom view) 0.20 ref 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 12 max top view 0.60 max 0.60 max pin 1 indicator 0.50 ref pin 1 indicator 0.25 min 7.10 7.00 sq 6.90 6.85 6.75 sq 6.65 figure 85. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9255bcpz-125 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 AD9255bcpzrl7-125 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 AD9255bcpz-105 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 AD9255bcpzrl7-105 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 AD9255bcpz-80 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 AD9255bcpzrl7-80 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 AD9255-125ebz evaluation board AD9255-105ebz evaluation board AD9255-80ebz evaluation board 1 z = rohs compliant part. AD9255 rev. a | page 42 of 4 4 notes AD9255 rev. a | page 43 of 4 4 notes AD9255 rev. a | page 44 of 44 notes ?2009C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08505-0-1/10(a) |
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